library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; 
use ieee.std_logic_arith.all; 

entity alu is
port (  a, b 		: in std_logic_vector(31 downto 0);
		alucontrol  : in std_logic_vector(2 downto 0);
        y 			: out std_logic_vector(31 downto 0);
        zero 		: out std_logic);
end entity;

architecture arch of alu is
begin
    process (alucontrol, a, b)
    variable res : std_logic_vector(31 downto 0);	
    begin
    	--y <= x"00000000";
    	case alucontrol is
        	when "000" =>
		   		res := a and b;
		    when "001" =>
		    	res := a or b;
		    when "010" =>
		    	res := a + b;
		    when "100" =>
		   		res := a and (not b);
		    when "101" =>
		   		res := a or (not b);
		    when "110" =>
		    	res := a - b;
		    when "111" =>
		    	if (unsigned(a) < unsigned(b)) then
		    		res := x"00000001";
		    	else
		    		res := (others => '0');
		    	end if;
		    when others =>
		    	-- ¡¡NADA!!
        end case;
        if (unsigned(res) = 0) then
        	zero <= '1';
        else
        	zero <= '0';
        end if;
   		y <= res;
    end process;
end architecture;
